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JUN. 2000 Ver 0.3
DATA SHEET
KB2512 Preliminary
KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
DEFLECTION PROCESSOR
32-SDIP-400
The KB2512 is a monolithic integrated circuit assembled in 32 pins shrunk dual in line plastic package. This IC controls all the functions related to the horizontal and vertical deflection in multi modes or multifrequency computer display monitors. The internal sync processor, combined with the very powerful geometry correction block make the KB2512 suitable for very high performance monitors with very few external components. The horizontal jitter level is very low. It is particularly well suited for high-end 17" and 19" monitors.
FUNCTIONS ORDERING INFORMATION
* * * * * Deflection processor I2C bus control B+ regulator Vertical parabola generator Vertical dynamic focus * *
KB2512 32-SDIP-400 Device Package Operating Temperature 0 C ~ 70 C
FEATURES
(HORIZONTAL) * * * * * Self-adaptive Dual PLL concept 150kHz maximum frequency X-RAY protection input I2C controls: Horizontal duty-cycle, H-position, free running frequency, frequency generator for burn-in mode.
Horizontal dynamic phase (side pin balance & parallelogram) Vertical dynamic focus (Vertical focus amplitude)
(GENERAL) * * * * * * Sync processor 12V supply voltage Hor. & Vert. lock/unlock outputs Read/Write I2C interface Horizontal and vertical moire B+ Regulator - Internal PWM generator for B+ current mode step-up converter. - I2C adjustable B+ reference voltage - Output pulses synchronized on horizontal frequency - Internal maximum current limitation. - Soft start * Compared with the KB2511B, KB2512 HAS: - Corner correction - Horizontal moire - B+ soft start - Increased max. Vertical frequency - No horizontal focus - No step down option for DC/DC converter.
(VERTICAL) * * * * * Vertical ramp generator 50 to 185Hz AGC loop Geometry tracking with V-POS & V-AMP I2C Controls: V-AMP, V-POS, S-CORR, C-CORR DC breathing compensation
(I2C GEOMETRY CORRECTIONS) * Vertical parabola generator (pincushion-E/W, keystone, corner)
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
BLOCK DIAGRAM
H POSITION
HLOCKOUT
PLL2C
PLL1F
7
8
3
6
5
12
4
HREF
13
VR EF
HGND
11
PHASE/ FREQUENCY COMPARATOR H-PHASE(7 bits)
VCO
PHASE COMPARATOR
PHASE SHIFTER
H-DUTY (5 bits)
HOUT BUFFER
LOCK/UNLOCK IDENTIFICATION
Forced Freq. 2 bits Free running 5 bits
HOUT 26
HFLY
R0
C0
SAFETY PROCESSOR
5V Vcc XRAY B+ ADJUST 7 bits B+ CONTROLLER
14 28 15 16 HSYNC 17
COMP B+ OUT REGIN
H/HVIN
1 SYNC INPUT SELECT (1bit) SYNC PROCESSOR
X2 Spin Bal 6 bits X2 Key Bal 6 bits Horizontal Moire Cancel 5 bits + on/off
VSYNCIN
ISENSE BGND
2
+
VCC
29
VSYNC
9
HMOIRE
XRAY
25 MOIRE CANCEL 5 BITS+ON/OFF GEOMETRY TRACKING 6 bits 8 bits VAMP 7 bits S AND C CORRECTION I 2 C INTERFACE + VERTICAL OSCILLATOR RAMP GENERATOR 10 Corner 7 bits X4 EW 7 bits X2 keyst 6 bits X AMPVDF 6 bits FOCUS
VREF
21
VR EF
VGND
19
5V
32
RESET GENERATOR
+
SDA
31
SCL
30
GND
27 VPOS 7bits
22 VCAP
20 VACCAP
18 BREATH
23 VOUT
24 EWOUT
2
KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PIN CONFIGURATIONS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
H/HVIN VSYNCIN HLOCKOUT PLL2C C0
5V SDA SCL VCC BOUT
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
PLL1F HPOSITION HMOIRE FOCUSOUT HGND HFLY HREF COMP REGIN ISENSE
KB2512
R0
GND HOUT XRAY EWOUT VOUT
VCAP VREF VAGCCAP VGND BREATH B+GND
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
PIN DESCRIPTION
Table 1. Pin Description No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pin Name H/HVIN VSYNCIN HLOCKOUT PLL2C C0 R0 PLL1F HPOSITION HMOIRE FOCUSOUT HGND HFLY HREF COMP REGIN ISENSE B+GND BREATH VGND VAGCCAP VREF VCAP VOUT Description TTL compatible horizontal sync input (separate or composite) TTL compatible vertical sync input (for separated H&V) First PLL lock/unlock output (0V unlocked - 5V locked) Second PLL loop filter Horizontal oscillator capacitor Horizontal oscillator resistor First PLL loop filter Horizontal position filter (capacitor to be connected to HGND) Horizontal moire output (to be connected to PLL2 C through a resistor divider) Vertical dynamic focus output Horizontal section ground Horizontal Flyback input (positive polarity) Horizontal section reference voltage (to be filtered) B+ error amplifier output for frequency compensation and gain setting Regulation input of B+ control loop Sensing of external B+ switching transistor current Ground (related to B+ reference adjustment) DC breathing input control (compensation of vertical amplitude against EHV variation) Vertical section ground Memory capacitor for automatic gain control loop in vertical ramp generator Vertical section reference voltage (to be filtered) Vertical sawtooth generator capacitor Vertical ramp output (with frequency independent amplitude and S or C corrections if any). It is mixed with vertical position voltage and vertical moire. Pincushion-East/West correction parabola output X-RAY protection input (with internal latch function) Horizontal drive output (internal transistor, open collector) General ground (referenced to Vcc) B+ PWM regulator output Supply voltage (12V typ) I2C clock input I2C data input Supply voltage (5V typ)
24 25 26 27 28 29 30 31 32
EWOUT XRAY HOUT GND BOUT Vcc SCL SDA 5V
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KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
REFERENCE DATA
Table 2. Reference Data Parameter Horizontal frequency Autosynch frequency (for given R0 and C0) Horizontal sync polarity input Polarity detection (on both horizontal and vertical section) TTL composite sync Lock/unlock identification (on both horizontal 1st PLL and vertical section) I2C control for H-position XRAY protection I2C horizontal duty cycle adjust I2C free running frequency adjustment Stand-by function Dual polarity H-drive outputs Supply voltage monitoring PLL1 inhibition possibility Blanking output Vertical frequency Vertical Autosync (for 150nf on pin22 and 470nf on pin20) Vertical S correction Vertical C correction Vertical amplitude adjustment DC breathing control on vertical amplitude Corner correction East/West parabola output (also known as pin cushion output) East/West correction amplitude adjustment Keystone adjustment Vertical position adjustment Internal dynamic horizontal phase control Side pin balance amplitude adjustment Parallelogram adjustment Tracking of geometric corrections with vertical amplitude and position Reference voltage (both on horizontal and vertical) Value 15 to 150 1 to 4.5FO Yes Yes Yes Yes 10 Yes 30 to 60 0.8 to 1.3FO Yes No Yes No No 35 to 200 50 to 185 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Hz Hz % FH % Unit kHz FH
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
Table 2. Reference Data (Continued) Parameter Vertical dynamic focus I2C horizontal dynamic focus amplitude adjustment I2C horizontal dynamic focus symmetry adjustment I2C vertical dynamic focus amplitude adjustment Deflection of input sync type Vertical moire output Horizontal moire output I2C controlled moire amplitude Frequency generator for burn-in Fast I2C read/write B+ regulation adjustable by I2C B+ soft start Value Yes No No Yes Yes Yes Yes Yes Yes 400 Yes Yes kHz Unit
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KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings No 1 2 3 Supply voltage (Pin 29) Supply voltage (Pin 32) Maximum voltage on Pin 4 Pin 5 Pin 6, 7, 8, 14, 15, 16, 20, 22 Pin 9, 10, 18, 23, 24, 25, 26, 28 Pin 1, 2, 3, 30, 31 ESD susceptibility Human body model, 100pF discharge through 1.5K EIAJ norm, 200pF discharge through 0 Storage temperature Operating temperature Item Symbol VCC VDD VIN Value 13.5 5.7 4.0 6.4 8.0 VCC VDD 2 300 Tstg Topr - 40, +150 0, +70 Unit V V V V V V V kV V C C
4
VESD
5 6
THERMAL CHARACTERISTICS
Table 4. Thermal Characteristics No 1 2 Junction temperature Junction-ambient thermal resistance Item Symbol Tj ja Value +150 65 Unit C C/W
SYNC PROCESSOR
OPERATING CODNITIONS(VDD = 5V, Tamb = 25 C) Table 5. Sync Processor Operating Conditions Parameter Horizontal sync input voltage Minimum horizontal input pulse duration Maximum horizontal input signal duty cycle Vertical sync input voltage Minimum vertical sync pulse width Maximum vertical sync input duty cycle Maximum vertical sync width on TTL H/V composite Sink and source current Symbol HsVR MinD Mduty VsVR VSW VSmD VextM IHLOCKOUT Conditions Pin 1 Pin 1 Pin 1 Pin 2 Pin 2 Pin 2 Pin 1 Pin 3 0 5 15 750 250 Min 0 0.7 25 5 Typ Max 5 Unit V s % V s % s A
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
ELECTRICAL CHARACTERISTICS (VDD = 5V, Tamb = 25 C) Table 6. Sync Processor Electrical Characteristics Parameter Horizontal and vertical input threshold voltage (pin 1, 2) Horizontal and vertical pull-up resister Falling and rising output CMOS buffer Horizontal 1st PLL lock output status (pin 3) Extracted Vsync integration time (% of TH (see 9)) on H/V composite Symbol VINTH RIN TfrOut VHlock Conditions Low level High level Pins 1,2 Pin 3, Cout = 20pF Locked, ILOCKOUT = -250A Unlocked, I LOCKOUT = +250A VoutT C0 = 820pF 4.4 26 0 5 35 Min 2.2 200 200 0.5 Typ Max 0.8 Unit V V K ns V V %
I2C READ/WRITE (See also I2C table control and I2C sub address control)
OPERATING CONDITIONS (VDD = 5V, Tamb = 25 C) Table 7. I2C Read/Write Operating Conditions Parameter Input high level voltage Input low level voltage Hold time before a new transmission can start Hold time for start conditions Set-up time for stop conditions Hold time data Set-up time data Rise time of SCL Fall time of SCL Maximum clock frequency Low period of the SCL clock High period of the SCL clock SDA and SCL input threshold Acknowledge output voltage on SDA input with 3mA Symbol VinH VinL tBUF tHDS tSUP tHDAT tSUPDAT tR tF Fscl Tlow Thigh Vinth VACK Pin 30 Pin 30 Pin 30 Pin 30, 31 Pin 31 1.3 0.6 2.2 0.4 Condition Min 3.0 0 1.3 0.6 0.6 0.3 0.25 Typ Max 5.0 1.5 1.0 3.0 400 Unit V V s s s s s s s kHz s s V V
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KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
I2C Bus Timing Requirement
tBUF
Start:Clock High
tHDAT
Stop:Clock High
SDA tHDS SCL tSUPDAT tSUP
tHIGH Data Change:Clock Low
tLOW
HORIZONTAL SECTION
OPERATING CONDITIONS Table 8. Horizontal Section Operating Conditions Parameter VCO Minimum oscillator resistor Minimum oscillator capacitor Maximum oscillator frequency OUTPUT SECTION Maximum input peak current Horizontal drive output maximum current I12m HOI Pin 12 Pin 26, sunk current 5 30 mA mA Ro(Min.) Co(Min.) Fo(Max.) Pin 6 Pin 5 6 390 150 K pF kHz Symbol Conditions Min Typ Max Unit
ELECTRICAL CHARACTERISTICS (VDD = 5V, Tamb = 25 C) Table 9. Horizontal Section Electrical Characteristics Parameter SUPPLY AND REFERENCE VOLTAGE Supply voltage Supply voltage Supply current Supply current Horizontal reference voltage Vertical reference voltage Vcc VDD ICC IDD VREF-H VREF-V Pin 29 Pin 32 Pin 29 Pin 32 Pin 13, I = -2mA Pin 21, I = -2mA 7.4 7.4 10.8 4.5 12 5 50 5 8 8 8.6 8.6 13.2 5.5 V V mA mA V V Symbol Conditions Min Typ Max Unit
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
Table 9. Horizontal Section Electrical Characteristics (Continued) Parameter Max. sourced current on VREF-H Max. sourced current on VREF-V 1st PLL SECTION Polarity integration delay VCO control voltage (pin 7) HpoIT VVCO Pin 1 VREF-H = 8V fo fH (Max.) VCO gain (pin 7) VCOG Ro = 6.49K, Co = 820pF, dF/dV = 1/11RoCo % of horizontal period Sub-address 01 Hphmin Hphtyp Hphmax IPII1U IPII1L fo Byte x 1111111 Byte x 1000000 Byte x 0000000 PLL1 is unlocked PLL1 is locked Ro = 6.49K, Co = 820pF, fo = 0.97/8RoCo 2.8 3.4 4.0 140 1 22.8 -150 Sub-address 02 Byte x x x 11111 Byte x x x 00000 Ro = 6.49K, Co = 820pF, from fo + 0.5kHz to 4.5Fo (fo:22.8kHz) fH (min.) fH (max.) Sub-address 02 2F0 3F0 FBth Hjit At 31.4kHz 0.65 0.75 70 V ppm V V V A mA kHz ppm/c 1.3 6.2 17 V V kHz/V 0.75 ms Symbol IREF-H IREF-V Conditions Pin 13 Pin 21 Min Typ Max 5 5 Unit mA mA
Horizontal phase adjustment (see 11) Horizontal phase setting value (Pin 8)
(see 11)
Hph
10
%
Minimum current value Typical value Maximum value PLL1 filter current charge Free running frequency
Free running frequency thermal drift (no drift on external components)
(see 7)
dF0/dT
Free running frequency adjustment Minimum value Maximum value PLL1 capture range
fo(Min.) fo(Max.) CR
0.8 1.3
Fo Fo
23.5 100
kHz kHz
Safe forced frequency SF1 Byte 11 x x x x x x SF2 Byte 10 x x x x x x Flyback input threshold voltage (pin12) Horizontal jitter
SFF
2ND PLL SECTION HORIZONTAL OUTPUT SECTION
10
KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Table 9. Horizontal Section Electrical Characteristics (Continued) Parameter Horizontal drive output duty-cycle (pin 26) (see 1) Low level High level X-RAY protection input threshold voltage Internal clamping levels on 2nd PLL loop filter (pin 4) Threshold voltage to stop H-out, V-out, B-out and XRAY when VCC < VSCinh Threshold voltage to stop H-out, V-out, B-out and reset XRAY when VDD < VSDinh Horizontal drive output (low level) HDmin HDmax XRAYth Vphi2 VSCinh VSDinh Symbol Conditions Sub-address 00 Byte xxx11111 Byte xxx00000 (see 2) Pin 25 (see 12) Low level High level Pin 29 Pin 32 30 60 8 1.6 4.0 7.5 4.0 % % V V V V V Min Typ Max Unit
HDvd
Pin 26 IOUT = 30mA RLOAD = 10K, Pin 10 2
200
0.4
V
VERTICAL DYNAMIC FOCUS FUNCTION (POSITIVE PARABOLA) Bottom DC output level DC output voltage thermal drift (see 17) Vertical dynamic focus parabola amplitude with VAMP and VPOS typical Min. Byte 000000 Typ. Byte 100000 Max. Byte 111111 Parabola amplitude function of VAMP (tracking between VAMP and VDF) with VPOS typ. (Figure 1) (see 3) Parabola asymmetry function of VPOS control (tracking between VPOS and VDF) with VAMP Max. HDFDC TDHDF AMPVDF Sub-address 0F 0 0.5 1 VDFAMP Sub-address 05 Byte 10000000 Byte 11000000 Byte 11111111 Sub-address 06 Byte x0000000 Byte x1111111 0.6 1 1.5 0.52 0.52 Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp V
ppm/C
VHDFKeyt
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
VERTICAL SECTION
OPERATING CONDITIONS Table 10. Vertical Section Operating Conditions Parameter OUTPUTS SECTION Maximum EW output voltage Minimum EW output voltage Minimum load for less than 1% vertical amplitude drift VEWM VEWm RLOAD Pin 24 Pin 24 Pin 20 1.8 65 6.5 V V M Symbol Conditions Min Typ Max Unit
ELECTRICAL CHARACTERISTICS (VCC = 12V, TAMB = 25 C) Table 11. Vertical Section Electrical Characteristics Parameter VERTICAL RAMP SECTION Voltage at ramp bottom point Voltage at ramp top point (with sync) Voltage at ramp top point (without sync) Vertical sawtooth discharge time duration (pin 22) Vertical free running frequency see (see 4) VRB VRT VRTF VSTD VFRF VREF-V = 8V, Pin 22 VREF-V = 8V, Pin 22 Pin 22 With 150nF cap
COSC (pin22) =150nF
VRT-0.1
Symbol
Conditions
Min
Typ 2 5
Max
Unit V V V s Hz
70 100
measured on pin 22 AUTO -SYNC frequency (see 13) Ramp amplitude drift versus frequency at Maximum vertical amplitude Ramp linearity on pin 22 (I22/I22) (see 4) Vertical position adjustment voltage (pin 23 - VOUT centering) ASFR RAFD RIin Vpos C22=150nF 5% C22 = 150nF 50Hz < f < 185Hz 2.5 < V22 < 4.5V Sub address 06 Byte x0000000 Byte x1000000 Byte x1111111 Sub address 05 Byte x0000000 Byte x1000000 Byte x1111111 0.5 3.2 3.5 3.8 2.25 3 3.75 5 3.3 50 200 185 Hz ppm/ Hz % V V V V V V mA
3.65
Vertical output voltage (peak-to-peak on pin 23)
VOR
2.5
3.5
Vertical output maximum current (pin 23)
VOI
12
KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Table 11. Vertical Section Electrical Characteristics (Continued) Parameter Max vertical S-correction amplitude (see 14) XOXXXXXX inhibits S-CORR X1111111 gives max S-CORR Vertical C-Corr amplitude XOXXXXXX inhibits C-corr Symbol dVS Conditions Sub address 07 V/Vpp at TV/4 V/Vpp at 3TV/4 Sub address 08 V/Vpp at TV/2 Byte X1000000 Byte X1100000 Byte X1111111 pin 24, see figure 2 Min Typ -4 +4 Max Unit % %
Ccorr
-3 0 3 2.5 100
% % % V ppm/ C Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp
EAST/WEST FUNCTION DC output voltage with typ. Vpos, keystone and corner inhibited DC output voltage thermal drift Parabola amplitude with max. Vamp, typ. V-Pos, keystone and corner inhibited EWDC
TDEWDC see note 7 EWpara Sub address 0A Byte 1111111 Byte 1100000 Byte 1000000 Sub address 05 Byte 1000000 Byte 1100000 Byte 1111111 Sub address 09 Byte 1x000000 Byte 1x111111 Sub address 06
1.7 0.85 0 0.30 0.55 0.85 0.65 0.65
Parabola amplitude function of V-AMP control (tracking between V-AMP and E/W) with typ. Vpos, typ. EW amplitude, keystone and corner inhibited (see 8) Keystone adjustment capability with typ.Vpos, corner and E/W inhibited and max. vertical amplitude. (see 8) Intrinsic keystone function of V-POS control (tracking between V-pos and EW) max. E/W and max. vertical amplitude and corner inhibited. (see 7) A/B ratio B/A ratio Corner amplitude with max. VAMP, typ. VPOS, keystone and E/W inhibit
EWtrack
KeyAdj
KeyTrack
Byte x0000000 Byte x1111111 Corner Sub address 0B Byte 11111111 Byte 11000000 Byte 10000000
0.52 0.52 1.7 0 -1.7 Vpp Vpp Vpp
INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION Side pin balance parabola amplitude (Figure3) with max. Vamp, typ. V-POS and parallelogram inhibited (see 8, 9) SPBpara Sub address 0D Byte x1111111 Byte x1000000 +1.4 -1.4 %T H %T H
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
Table 11. Vertical Section Electrical Characteristics (Continued) Parameter Side pin balance parabola amplitude function of Vamp control (tracking between Vamp and SPB) with max. SPB, typ. V-POS and parallelogram inhibited (see 8, 9) Parallelogram adjustment capability with max. Vamp, typ. V-POS and max. SPB (see8, 9) Intrinsic parallelogram function of Vpos control (tracking between V-pos and DHPC) with max. Vamp, max. SPB and parallelogram inhibited
(see 8, 9)
Symbol
Conditions
Min
Typ 0.5 0.9 1.4 +1.4 -1.4
Max
Unit %T H %T H %T H %T H %T H
SPBtrack Sub address 05 Byte 10000000 Byte 11000000 Byte 11111111 ParAdj Sub address 0E Byte x1111111 Byte x1000000 Sub address 06
Partrack
A/B ratio B/A ratio VERTICAL MOIRE Vertical moire (measured on VOUT) pin 23 BREATHING COMPENSATION DC breathing control range (see 15) Vertical output variation versus DC breathing control (Pin 23)
BRRANG VMOIRE
Byte x0000000 Byte x1111111
0.52 0.52
Sub address 0C
Byte 01x11111
6 1 0 -10 12
mV V % %
V18 V18 VREF-V V18 = 4V
BRADj
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KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
B+ SECTION
OPERATING CONDITIONS Table 12. B+ Section Operating Conditions Parameter Minimum feedback resistor Symbol Conditions Min 5 Typ Max Unit K
FeedRes Resistor between pins 15 and 14
ELECTRICAL CHARACTERISTICS (VCC = 12V, Tamb = 25 C) Table 13. B+ Section Electrical Characteristics Parameter Error amplifier open loop gain Sunk current on error amplifier output when BOUT is in safety condition Unity gain band width Regulation input bias current Maximum guaranteed error amplifier output current Current sense input voltage gain Max current sense input threshold voltage Current sense input bias current Maximum external power transistor on time B+ output saturation voltage Internal reference voltage Symbol OLG Icomp UGBW IRI EAOI CSG MCEth ISI Tonmax B+OSV IVREF Conditions At low frequency Pin 14 (see 12)
(see 7) (see 10)
Min
Typ 85 0.5 6 0.2
Max
Unit dB mA MHz A
Current sourced by pin 15 (PNP base) Current sourced by pin 14 Current sunk by pin 14 Pin 16 Pin 16 Current sourced by pin 16 (PNP base) % of H-period @ fo = 27kHz
(see 6)
0.5 2 3 1.2 1 100 0.25 4.8
mA mA V A % V V
V28 with I28 = 10mA On error amp positive input for subaddress 0B Byte 1000000 Byte 111111 Byte 000000 Pin 28
Internal reference voltage adjustment range Falling time
VREFADJ tFB+
+20 -20 100
% % ns
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Duty cycle is the ratio of power transistor off time period. Power transistor is off when output transistor is off. Initial condition for safe operation start up. S and C correction are inhibited so the output sawtooth has a linear shape. With register 07 at byte x0xxxxxx (s-correction is inhibited) then the S correction is inhibited, and with register 08 at byte x0xxxxxx (C-Correction is inhibited) consequently the sawtooth has a linear shape. These parameters are not tested on each unit. They are measured during our internal qualification. The external power transistor is OFF during 400ns. These parameters are not tested on each unit. They are measured during out internal qualification. Refers to notes 4. TH is the Horizontal period. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches coming from corners of our processes and also temperature characterization. See Figure 7 for explanation of reference phase. See Figure 11. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on Pin 22 and with a constant ramp amplitude. TV is the vertical period. When not used the DC breathing control pin must be connected to 12V.
CAUTIONS: The ICS near CDT can be latched up by EHT. Therefore, in order to minimize the impact of the EHT, it is necessary to place ICs far from CDT.
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KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
VDFAMP B
A
VDFDC
Figure 1. Vertical Dynamic Focus Function
EWPARA B
A
EWDC
Figure 2. E/W Output
B
A
SPBPARA DHPCPC
Figure 3. Dynamic Horizontal Phase Control Output
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
Table 14. Typical Vertical Output Wave forms Function Vertical Size Sub Address 05 Pin 23 10000000 Byte Specification Picture Image
VOUTDC 2.25V VOUTDC 3.75V
11111111 Vertical Position DC Control 06 23 x0000000 x1000000 x1111111 3.2V 3.5V 3.8V
Vertical S Linearity
07
23 x0xxxxxx Inhibited V Vpp V =4% Vpp V Vpp V Vpp x1111111 V =3% Vpp V =3% Vpp
x1111111 Vertical C Linearity 08 23 x1000000
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KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Table 15. Geometry Output Wave forms Function Key stone (trapezoid) control Sub address 09 Pin 24 Byte E/W + corner inhibited
0.65V 2.5V
Specification
Picture Image
1x000000 1x111111
0.65V 2.5V
E/W (pin cushion) control
0A
24
Keystone + corner Inhibited
2.5V 0V
10000000 1111111
1.7V
Corner control
0B
24
Keystone + E/W inhibited 11111111 10000000
1.7V 2.5V 1.7V
Parallelogram control
0E
Internal
SPB Inhibited 1x000000
3.7V
1.4% TH
3.7V
1.4% T H
1x111111 Side pin balance control 0D Internal Parallelogram Inhibited
3.7V 1.4% TH 1.4% TH
1x000000 1x111111 Vertical dynamic focus OF 10
3.7V
2V TV
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
I2C BUS ADDRESS TABLE
Slave address (8C): Write mode Sub address definition Table 16. I2C Bus Address Table D8 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Horizontal drive selection/horizontal duty cycle Horizontal position Forced Frequency/free running frequency Synchro priority/horizontal moire amplitude Refresh/B+ reference adjustment Vertical ramp amplitude Vertical position adjustment S correction C correction E/W keystone E/W amplitude E/W corner adjustment Vertical moire amplitude Side pin balance Parallelogram Vertical dynamic focus amplitude
Slave address (8D): Read mode No sub address needed
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Table 17. I 2C Bus Address Table (continued)
D8 D7 D6 D5 WRITE MODE 00 HDrive 0: off [1]: on Xray 1: reset [0] Forced frequency 1: on [0]: off 03 Sync 0: comp [1]: sep Detect refresh [0]: off Vramp 0: off [1]: on 1: F0x2 [0]: F0x3 HMoire 1: on [0] [0] [0] Horizontal duty cycle [0] [0] Horizontal phase adjustment [1] [0] [0] [0] [0] Free running frequency [0] Horizontal moire amplitude [0] [0] [0] B+ reference adjustment [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] D4 D3 D2 D1
01
02
04
05
Vertical ramp amplitude adjustment [1] [0] [0] [0] Vertical position adjustment [1] [0] [0] [0] S correction [1] [0] [0] C correction [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]
06
07
S Select 1: on [0] C Select 1: on [0] EW key 0: off [1]
08
09
East/west keystone [1] [0] [0] East/west amplitude [1] [0] [0] [0] East/west corner adjustment [1] Vmoire 1: on [0] [0] [0] [0] [0] Vertical moire [0] [0] Side pin balance [1] [0] [0] Parallelogram [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]
0A
0B
E/W cor 0: off [1] Test V 1: on [0]: off SPB sel 0: off [1] Parallelogram 0: off [1] Test H 1: on [0]: off
0C
0D
0E
0F
Vertical dynamic focus amplitude [1] [0] READ MODE [0] [0] [0] [0]
00
Hlock 0: on [1]: no
Vlock 0: on [1]: no
Xray 1: on [0]: off
Polarity detection H/V pol [1], negative V pol [1], negative Vext det [0], no det
Synchro detection H/V det [0], no det V det [0], no det
[ ] initial value Set the unspecified bit to [0] in order to assure the compatibility with future devices.
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
OPERATING DESCRIPTION
GENERAL CONSIDERATIONS Power Supply The typical values of the power supply voltages Vcc and VDD are respectively 12V and 5V. Perfect operation is obtained if Vcc and VDD are maintained in the limits: 10.8 to 13.2V and 4.5 to 5.5V. In order to avoid erratic operation of the circuit during the transient phase of Vcc and VDD switching on, or switching off, the value of Vcc and VDD are monitored and the outputs of the circuit are inhibited if Vcc is less than 7.5V typically. In the same manner, VDD is monitored and internal set-up is made until V DD reaches 4V (see I2C control table for power on reset). In order to have a very good power supply rejection, the circuit is internally powered by several internal voltage references (the typical value is 8V). Two of these voltage references are externally accessible, one for the vertical part and on one for the horizontal one. If needed, these voltage references can be used (until Iload is less than 5mA). Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connected to ground, in order to minimize the noise and consequently the "jitter" on vertical and horizontal output signals. I2C Control KB2512 belongs to the I2C controlled device family, instead of being controlled by DC voltage on dedicated control pins, each adjustment can be realized through the I2C interface. The I2C bus is a serial bus with a clock and a data input. The general function and the bus protocol are specified in the Phillips-bus data sheets. The interface (data and clock) is TTL-level compatible. The internal threshold levels of the input comparator are 2.2V on rising edge and 0.8V on falling edge (when VDD is 5V). Spikes of up to 50ns are filtered by an integrator and maximum clock speed is limited to 400kHz. The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply information (1byte) to the micro-processor. The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to transmit the IC-address (hexa 8C for write, 8D for read). Write Mode In write mode the second byte sent contains the sub address of the selected function to adjust (or controls to affect) and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automatically the momentary sub address in the sub address counter by one (auto-increment mode). So it is possible to transmit immediately the next data bytes without sending the IC address or sub address. It can be useful so as to reinitialize the whole controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for E/W correction, 2 for the dynamic horizontal phase control, 1 for moire option, 3 for horizontal and vertical dynamic focus and 1 for B+ reference adjustment. 17 bits are also dedicated to several controls (on/off, horizontal forced frequency, sync priority, detection refresh and XRAY reset).
22
KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Read Mode During read mode the second byte transmits the reply information. The reply byte contains horizontal and vertical lock/unlock status, the XRAY activated or not, the horizontal and vertical polarity detection. It also contains the Synchro detection status which is used by the MCU to assign sync priority. A stop condition always stops all the activities of the bus decoder and switches to high impedance both the data and the clock line (SDA and SCL) . See I2C sub address and control tables. Sync processor The internal sync processor allows the KB2512 to accept any kind of input Synchro signals: * * Separated horizontal & vertical TTL-compatible sync signals, Composite horizontal & vertical TTL-compatible sync signals.
Sync identification Status The MCU can read (address read mode: 8D) the status register via the I2C bus, and then select the sync priority depending on this status. Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and (when 12V is supplied) whether a Vext has been extracted from H/HVIN. Both horizontal and vertical sync are detected even if only 5V is supplied. In order to choose the right sync priority the MCU may proceed as follows (see I2C address Table): * * * Refresh the status register, Wait at least for 20ms(max. vertical period), Read this status register,
Sync priority choice should be: Vext Det No Yes H/V Det Yes Yes V Det Yes No Sync Priority Subaddress 03 (D8) 1 0 Comment Sync Type Separated H & V Composite TTL H & V
Of course, when choice is made, one can refresh the sync detections and verify that extracted Vsync is present and that no sync change occurred. The Sync processor is also giving sync polarity information. IC status The IC can inform the MCU about the 1st horizontal PLL and vertical section status, and about the XARY protection (activated or not). Resetting the XRAY internal latch can be done either by decreasing the Vcc supply or directly resetting it via the I2C interface.
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
Sync Inputs Both H/HVin and Vsyncin inputs are TTL compatible trigger with Hysteresis to avoid erratic detection. Both inputs include a pull up register connected to VDD. Sync Processor Output The sync processor indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync. HLOCKOUT is a TTL compatible CMOS output. Its level goes to high when locked. In the same time the D8 bit of the status register is set to 0. This information is mainly used to trigger safety procedures (like reducing B+ value) as soon as a change is detected on the incoming sync. Further to this, it may be used in an automatic procedure for free running frequency(fo) adjustment. Sending the desired fo on the sync input and progressively decreasing the free running frequently I2C register value (address 02), the HLOCKOUT Pin will go high as soon as the proper setting is reached. Setting the free running frequency this way allows to fully exploit the KB2512 horizontal frequency range. HORIZONTAL PART Internal input conditions Horizontal part is internally fed by Synchro processor with a digital signal corresponding to horizontal Synchro pulses or to TTL composite input. concerning the duty cycle of the input signal, the following signals (positive or negative) may be applied to the circuit. Using internal integration, both signals are recognized on condition that Z/T < 25%, Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7s.
Z T
Z
An other integration is able to extract vertical pulse of composite Synchro if duty cycle is more than 25% (typically d = 35%) (see 7)
c
TRAMEXT
d
d
The last feature performed is the equalizing pulses removing to avoid parasitic pulse on phase comparator input which is intolerant to wrong or missing pulse.
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KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PLL1 The PLL1 is composed of a phase comparator, an external filter and a voltage control oscillator (VCO). The phase comparator is a phase frequency type designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a charge pump, composed of two current sources sunk and sourced (I = 1mA typ. when locked, I = 140A when unlocked). This difference between lock/unlock permits a smooth catching of horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is locked avoiding horizontal too fast frequency change. The dynamic behavior of the PLL is fixed by an external filter which integrates the current of the charge pump. A CRC filter is generally used (see Figure 4)
PLL1F 7
1.8K 4.7uF 1uF
Figure 4. PLL1
PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump and the filter (see Figure 5). The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the capacitor, by a current proportional to the current in the resistor. Typical thresholds of sawtooth are 1.6V and 6.4V.
H-LOCKOUT 3 Lockdet Input Interface Tramext High Comp1 E2 Low
Lock/Unlock Status
PLL1F R0 7 I2C Forced Frequency Tramext PLL Inhibition 6
C0 5
HSYNC 1
Charge PUMP
VCO I2C Hpos Adj. OSC
Phase Adjust
Figure 5. Block Diagram
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
I2C Free running Adjustment Loop Filter 7 a
+ -
ID 2
6.4V
+ -
ID 4 I0 2 5
1.6V
+ -
RS Flip Flop
(0.80(1.3V < V7 < 6V)
6 R0
6.4V
Co
1.6V
0 0.84T T
Figure 6. Details of VCO The control voltage of the VCO is typically comprised between 1.33V and 6V (see figure 6). The theoretical frequency range of this VCO is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to clamp intervention on filter lowest value. To avoid spread of external components and the circuit itself, it is possible to adjust free running frequency through I2C. This adjustment can be made automatically on the manufacturing line without manual operation by using lock/unlock information. The adjustment range is 0.8 to 1.3 F0 (where 1.3 F0 is the free running frequency at power on reset). The sync frequency has to be always higher than the free running frequency. As an example for a Synchro range from 24kHz to 100kHz, the suggested free running frequency is 23kHz. Another feature is the capability for MCU to force horizontal frequency throw I2C to 2xF0 or 3xF0 (for burn in mode or safety requirement). In this case, inhibition switch is opened leaving PLL1 free but voltage on PLL1 filter is forced to 2.66V for 2xF0 or 4.0V for 3xF0. The PLL1 ensures the coincidence between the leading edge of the Synchro signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage I2C adjustable between 2.8V and 4.0V (corresponding to 10%) (see Figure 7)
H osc Sawtooth
7/8TH
1/8TH 6.4V 2.8V < Vb < 4.0V Vb
Phase REF1 H Synchro
1.6V
Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.8V and 4.0V. The PLL1 ensures the exact coincidence between the signals phase REF and Hsyns. A TH/10 phase adjustment is possible
Figure 7. PLL1 Timing Diagram
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KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
The KB2512 also includes a lock/unlock identification block which senses in real time whether PLL1 is locked or not on the incoming horizontal sync signal. The resulting information is available on Hlockout (see sync processor). The block function is described in figure 5. When PLL1 is unlocked, It forces Hlockout to leave high. The lock/unlock information is also available throw I2C read. PLL2 The PLL2 ensures a constant position of the shaped Flyback signal in comparison with the sawtooth of the VCO (Figure 8). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output current:0.5mA). The Flyback input is composed of an NPN transistor. This input must be current driven. The maximum recommended input current is 5mA (see Figure 9). The duty cycle is adjustable through I2C from 30% to 60%. For start up safe operation, initial duty cycle (after power on reset) is 60% in order to avoid having a too long conduction period of the horizontal scanning transistor. The maximum storage time (Ts max.) is (0.44TH-TFLY/2). Typically, TFLY/TH is around 20% which means that Ts max is around 34% of TH.
H osc Sawtooth
7/8TH
1/8TH 6.4V 3.7V
1.6V Flyback Internally Shaped Flyback H drive Ts Duty Cycle
Figure 8. PLL2 Timing Diagram
400 HFLY 12 20K Q1
GND 0V
Figure 9. Flyback Input Electrical Diagram
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
Output Section The H-drive signal is transmitted to the output through a shaping block ensuring TS and I2C adjustable duty cycle. In order to secure scanning power part operation, the output is inhibited in the following circumstances: * * * * Vcc and VDD too low XRAY protection activated During horizontal Flyback H Drive I2C bit control is off.
The output stage is composed of a NPN bipolar transistor. Only the collector is accessible (see Figure 10).
26 H-DRIVE
Figure 10. Output Section
The output NPN is in off-state when the power scanning transistor is also in off-state. The maximum output current is 30mA, and the corresponding voltage drop of the output VCEsat is 0.4V Max. It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be designed between the circuit and the power transistor which can be of bipolar or MOS type. X-RAY Protection The activation of the X-ray protection is obtained by application of a high level on the X-ray input (8V on pin 25). It inhibits the H-drive and B+ outputs. This protection is latched; It may be reset either by Vcc or VDD switch off or by I2C (see Figure 11). Vertical Dynamic Focus The KB2512 delivers a vertical parabola wave from on pin 10. Vertical dynamic focus is tracked with VPOS and VAMP. Its amplitude can be adjusted. It is also affected by S and C corrections. This positive signal once amplified has to be connected to the CRT focusing grids.
28
KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
VCC Checking VCC + VSCinh VDD Checking VDD + VSDinh XRAY Protection XRAY S Q 2C Reset VCC or VDD off or I R Horizontal Flyback 0.7V +
I2C Drive on/off Horizontal Output Inhibition
I2C Ramp on/off Vertical Output Inhibition
Bout
Figure 11. Safety Functions Block Diagram VERTICAL PART Geometric Corrections The principle is represented in Figure 12.
V.Focus amp
2
VDCMID (3.5V)
23
I
10
Dynamic Focus
Vertical Ramp VOUT
EW + amp
2
+ VDCMID (3.5V)
Corner
+
Parabola Generator
24 Keystone
EW Output
VDCMID (3.5V)
Side pin amp
+
To Horizontal Phase Side pin Balance Output Current
Parallelogram
Figure 12. Geometric Corrections Principle
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
Starting from the vertical ramp, a parabola shaped current is generated for E/W correction, dynamic horizontal phase control correction, and vertical dynamic focus correction. The base of the parabola generator is an analog multiplier, the output current of which is equal to: I = k x (VOUT - VDCMID)2 Where Vout is the vertical output ramp (typically between 2 and 5V) and VDCMID is 3.5V (for V REF-V = 8V). One more multiplier provides a current proportional to (Vout - VDCMID)4 for corner correction The VOUT sawtooth is typically centered on 3.5V. By changing the vertical position, the sawtooth shifts by 0.3V. In order to keep a good screen geometry for any end user preference adjustment we implemented the geometry tracking. Due to large output stages voltage range (E/W, keystone corner), the combination of tracking function with maximum vertical amplitude max or min vertical position and maximum gain on the DAC control may lead to the output stages saturation. This must be avoided by limiting the output voltage by appropriate I2C registers values. For E/W part and dynamic horizontal phase control part, a sawtooth shaped differential current in the following form is generated: I' = k' x (V OUT - VDCMID)2 Then I and I'are added together and converted into voltage for the E/W part. Each of the three E/W components and the two dynamic horizontal phase control ones may be inhibited by their own I2C select bit. The E/W parabola is available on pin 24 by the way of an emitter follower which has to be biased by an external resistor (10K). It can be DC coupled with external circuitry. The vertical dynamic focus is available on output pin 10. Dynamic horizontal phase control current drives internally the H-position, moving the Hfly position on the horizontal sawtooth in the 1.4% The both on side pin balance and parallelogram. EW EWOUT = 2.5V + K1 (VOUT - VDCMID) + K2 (VOUT - VDCMID)2 + K3 (Vout - VDCMID)4 K1 is adjustable by the keystone I2C register K2 is adjustable by the EW amplitude I2C register K3 is adjustable by the corner I2C register Dynamic Horizontal Phase Control IOUT = K4 (VOUT - VDCMID) 2 + K5 (VOUT - VDCMID) K4 is adjustable by side pin balance I2C register K5 is adjustable by parallelogram I2C register. Function When the Synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. Typical free running frequency can be calculated by:
fo ( Hz ) = 1.5 10
-5
1 -------------C OSC
30
KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
A negative or positive TTL level pulse applied on pin 2 (VSYNC) as well as a TTL composite sync on pin 1 can Synchronize the ramp in the range [fmin, fmax]. This frequency range depends on the external capacitor connected on pin 22. A capacitor in the range [150nF, 5%] is recommended for application in the following range: 50Hz to 185Hz. Typical maximum and minimum frequency, at 25C and without any correction (S correction or C correction), can be calculated by: f(Max.) = 3.5 x fo and f(Min.) = 0.33 x fo If S or C corrections are applied, these values are slightly affected. If a Synchronization pulse is applied, the internal oscillator is Automatically caught but the amplitude is no more constant. An internal correction is activated to adjust it in less than a half a second: the highest voltage of the ramp pin 22 is sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance amplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant. The read status register enables to have the vertical lock-unlock and the vertical sync polarity informations. It is recommended to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. A good stability of the internal closed loop is reached by a 470nF 5% capacitor value on pin 20 (VAGC)
CHARGE CURRENT
TRANSCONDUCTANCE AMPLIFIER REF
22 DISCH. +
SAMPLING 20 SAMP CAP
S CORRECTION
VS_AMP SUB07/6bits COR-C SUB08/6bits
OSC CAP
2
V-SYNC
SYNCHRO POLARITY
OSCILLATOR
C CORRECTION
+
-
Vlow
Switch Diech
23 VOUT 18 BREATH
VERT_AMP SUB05/7BITS VMOIRE SUB0C/5BITS VOSITION SUB06/7BITS
Figure 13. AGC Loop Block Diagram
31
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
I2C Control Adjustments Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are generated internally. Their amplitude are adjustable by their respective I2C register. They can also be inhibited by their select bit. The amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on pin 23 (VOUT) to drive an external power stage. The gain of this stage is typically 25% depending on its register value. The mean value of this ramp is driven by its own I2C register (vertical position). Its value is VPOS = 7/16 * VREF 300mV. Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the non-inverting input of booster should also derive from VREF-V to optimize the accuracy (see application diagram). Basic Equations In first approximation, the amplitude of the ramp on pin 23 (Vout) is: VOUT - VPOS = (VOSC - VDCMID) * (1 + 0.25 (VAMP) ) with: * VDCMID = 7/16*VREF (typically 3.5V, the middle value of the ramp on pin 22) * * * VOSC = V22 (ramp with fixed amplitude) VAMP = - 1 for minimum vertical amplitude register value and +1 for maximum VPOS is calculated by: VPOS = VDCMID + 0.3Vp with Vp equals -1 for minimum vertical position register value and +1 for maximum
The current available on pin 22 is: IOSC = 3 8 * VREF * C OSC * f
with COSC: capacitor connected on pin 22 f: synchronization frequency. Vertical Moire By using the vertical moire, VPOS can be modulated from frame to frame. This function is intended to cancel the fringes which appear when line to line interval is very close to the CRT vertical pitch. The amplitude of the modulation is controlled by register VMOIRE on address OC and can be switched - off via the control bit D7.
32
KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
DC/DC CONVERTER PART
This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the B+ voltage(roughly proportional to the horizontal frequency) necessary for the horizontal scanning. This DC/DC converter must be configured in step-up mode. It operates very similarly to the well known UC3842. Step-up Mode Operating description * * * The power MOS is switched-on at the middle of the horizontal Flyback. The power MOS is switched-off when its current reaches predetermined value. For this purpose, a sense resistor is inserted in its source. The voltage on this resistor is sent to pin16 (ISENSE). The feedback (coming either from the EHV or from the Flyback) is divided to a voltage close to 4.8V and compared to the internal 4.8V reference (IVREF). The difference is amplified by an error amplifier, the output of which controls the power MOS switch-off current.
Main Features * * * * Switching synchronized on the horizontal frequency B+ voltage always higher than the DC source Current limited on a pulse-by-pulse basis The DC/DC converter is disabled: - When VCC or VDD are too low, - When X-Ray protection is latched, - Directly through I2C bus. When disabled, BOUT is driven to GND by a 0.5mA current source. This feature allows to implement externally a soft start circuit.
*
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2512
Iadjust
8V
DAC 7bits I2C
400ns
12V 4.8V 20%
+ 95dB A -
+ -
s
1/3 1.2V
C2 + C3 +
BOUT
S Q R
28
Soft start
1.2V
Inhibit SMPS
Inhibit SMPS
REGIN
COMP
ISENSE
15
14
1M
16 +
22K
L
V B+
Figure 14. DC/DC Converter Part
34
KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
APPLICATION BOARD CIRCUIT
VCC=12V
HSYNC
5V 1K 1 HSYNC_IN 5V 32 + 100uF 31 100 30 100 0.1uF SDA
VSYNC 1K 2 VSYNC_IN SDA
3
H_LOCKOUT
SCL
SCL
2
22nF 100V 4 1% P 820pF 50V 5
PLL2C
VCC
29 + 100uF 28 0.1uF 10K
CO
B+OUT
6.8K
6
RO
GND
27 1K
4.7uF 50V 1.8K 10nF 100V MP 1uF +
7
PLL1F
H_OUT
26 22K
HOUT
8
H_LOCKCAP
XRAY
25
50K
KB2512
2K 9 H MOIRE EWOUT 24 10K
10K
10
FOCUS
VOUT
23
10K
11 AFC 12 AFC 4.7uF 0.1uF 14 1M 22K 50K 22K 50K 3.3K 33K 15 + 16 13
HGND
VSCAP
22
150nF 100V 1% P
HFLY
V_REF
21 +47uF 50V 0.1uF
H_REF
VAGCCAP
20 470nF 63V P
COMP
VGND
19
10K
1K
50K REGIN HBLKOUT 18 1K I_SENSE B+GND 17
12V 1 SCLK 2 SDAT 1 3 ACK 2 4 3 4 5 6 7 12 11 10 9 8 SCL SDA + 0.1uF 100uF 6 7 8 11 10 9 10K 33pF AFC HOUT 4 5 13 13
74HCT125
5V 14 100K
47pF
1 2 3
16 15 47pF 14 100K
MC14528
12
Figure 15. Application Circuit
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